1. Field of the Invention
The present invention relates to a voltage conversion circuit used, for example, in the power supply of a liquid crystal panel and configured to output two voltages, that is, a positive and negative voltage, based on an input dc voltage.
2. Description of the Related Art
A first example of a voltage conversion circuit of this type according to the prior art (referred to below as first prior art circuit) is shown in FIG. 29.
As shown in FIG. 29 this first prior art circuit has a timing signal generator 1, MOS transistors Q1 to Q6 that are controllably switched ON/OFF by the output from the timing signal generator 1, capacitors C1 and C2 producing a positive voltage twice the dc input voltage Vin according to the ON/OFF operation of MOS transistors Q1 to Q4, capacitors C3 and C4 producing a negative voltage xe2x88x921 times the dc input voltage Vin according to the ON/OFF operation of MOS transistors Q1, Q2, Q5, and Q6, and a level shift circuit 2.
MOS transistors Q1 and Q5 of MOS transistors Q1 to Q6 are n-type, and MOS transistors Q2 to Q4 and Q6 are p-type. As shown in the figure, level shift circuit 2 consists of resistors, diodes, and the like.
Note also that the timing signal generator 1 and MOS transistors Q1 to Q4 enclosed in the dotted square in FIG. 29 in this first prior art circuit, are integrated onto a single semiconductor substrate forming an IC chip. The level shift circuit 2, MOS transistors Q5 and Q6, and capacitors C1 to C4 are separate components externally connected to the IC chip.
The operation of this first prior art circuit is described next with reference to FIG. 29 to FIG. 31.
The timing signal generator 1 generates and supplies timing signals (control signals) A, XB, XA2, XB2 to the gate of MOS transistors Q1 to Q4, respectively, to switch the MOS transistors Q1 to Q4 ON or OFF. Timing signals A and XB from timing signal generator 1 are level shifted by the level shift circuit 2, which outputs the resulting signals AS and XBS to the gates of MOS transistors Q5 and Q6 to switch MOS transistors Q5 and Q6 ON or OFF.
This operation causes MOS transistors Q1, Q3, Q5 to be ON and MOS transistors Q2, Q4, Q6 to be off in period T1 shown in FIG. 30. The circuit equivalent to operation period T1 is shown in FIG. 31A. Capacitor C1 is charged by the dc source Vin. The positive output voltage VOUT1 is the sum of the source voltage Vin and the stored charge voltage of capacitor C2. At the same time the charge of capacitor C3 is shared with capacitor C4, and the end voltage of capacitor C3 becomes the negative output voltage VOUT2.
In period T2 in FIG. 30 MOS transistors Q2, Q4, Q6 switch on, and MOS transistors Q1, Q3, Q5 switch off. The circuit equivalent to period T2 is shown in FIG. 31B. Capacitor C3 is charged by the dc source Vin, and the negative output voltage VOUT2 is the voltage across capacitor C4. At the same time, the charge of capacitor C1 is shared with capacitor C2, and the positive output voltage VOUT1 becomes the sum of the source voltage Vin and the stored charge voltage of capacitor C1. The voltage drops VF are due to the forward voltage drops of the diodes within the level shift circuit 2. This first prior art circuit thus operates as a charge-pump type dcxe2x80x94dc converter by simply repeating the operation of periods T1 and T2.
As a result of this operation, the values of positive output voltage VOUT1 and negative output voltage VOUT2 from this first prior art circuit can be determined from equations (1) and (2) where the ground GND potential is 0 V.
VOUT1=Vinxc2x72xe2x80x83xe2x80x83(1) 
VOUT2=Vinxc2x7(xe2x88x921)xe2x80x83xe2x80x83(2) 
where Vin is the dc input voltage.
FIG. 32 shows the configuration of the MOS transistors Q1 to Q4 inside the dotted line in FIG. 29 integrated to a semiconductor substrate in this first prior art circuit.
As shown in FIG. 32, reference numeral 11 is a p-type semiconductor substrate. An NMOS transistor Q1 with a source S, gate G, and drain D is formed in this p-type semiconductor substrate 12. Three n-wells 11 to 14 are also formed in p-type semiconductor substrate 11, and PMOS transistors Q2 to Q4 each having a source S, gate G, and drain D are formed in each of these n-wells 12 to 14.
Connections between parts of MOS transistors Q1 to Q4 and the p-type semiconductor substrate 11 are indicated by the bold lines in FIG. 32.
A second example of a voltage conversion circuit of this type according to the prior art (referred to below as second prior art circuit) is described next with reference to FIG. 33.
As shown in FIG. 33, this second prior art circuit replaces MOS transistors Q5 and Q6 of the first prior art circuit with diodes D1, D2, and eliminates the level shift circuit 2. The configuration of other parts is identical to the configuration of the first prior art circuit, and further description thereof is thus omitted.
Operation of this second prior art circuit is basically the same as that of the first prior art circuit except that since the switching devices are diodes, and not complementary MOS transistors, a voltage drop, VFa, equivalent to the forward voltage drop of the diodes is introduced at the output. Therefore, VOUT2 of this embodiment differs from that of the embodiment of FIG. 29 in that the negative output voltage VOUT2 is as shown in equation (3).
VOUT2=[Vinxc2x7(xe2x88x921)]+[VFaxc2x72]xe2x80x83xe2x80x83(3) 
where VFa is the forward voltage drop of diodes D1, D2.
A problem with the first prior art circuit as shown in FIG. 29 is that it is not possible to reduce the overall size of the circuit because of the many externally connected components, including parts of the level shift circuit 2 and MOS transistors Q5 and Q6.
Furthermore, because a level shift circuit 2 is needed, the level of timing signal A from timing signal generator 1 is gradually lowered by level shift circuit 2, resulting in signal AS (see FIG. 30) being applied to the gate of MOS transistor Q5. This drop increases if the frequency of signal AS is low, and potentially adversely affects the operation of MOS transistor Q5.
The second prior art circuit has an advantage over the first prior art circuit in that there are fewer external parts. However, the negative output voltage VOUT2 is decreased by the forward voltage VFa component of the diode as shown by equation (3), and power conversion efficiency thus drops.
Therefore, with consideration for the above problems, an object of the present invention is to provide a voltage conversion circuit that reduces the number of external parts as much as possible and thus enables an overall reduction in size while maintaining high power conversion efficiency.
To resolve the above problems, a voltage conversion circuit includes a plurality of MOS transistors that are switched ON/OFF to charge a capacitance with an input dc voltage, and this charging voltage is used to convert the input dc voltage to a specific positive and negative output voltage, wherein: the plural MOS transistors include PMOS and NMOS transistors for positive voltage conversion, and a NMOS transistor for negative voltage conversion; the NMOS transistors for positive voltage conversion are formed in a p-type semiconductor substrate; the PMOS transistors for positive voltage conversion are formed in an n-type first well formed in the p-type semiconductor substrate; and the NMOS transistor for negative voltage conversion is formed in a p-type third well, which is formed in an n-type second well formed in the p-type semiconductor substrate.
The present invention can thus form the MOS transistors used for voltage conversion in the same p-type semiconductor substrate, and can therefore reduce the external components to capacitors only. It is therefore possible to reduce the overall size while maintaining a high power conversion efficiency.
The present invention can alternatively be implemented as a voltage conversion circuit having a plurality of MOS transistors that are switched ON/OFF to charge a capacitance with an input dc voltage, and using this charging voltage to convert the input dc voltage to a specific positive and negative output voltage, wherein: the plural MOS transistors include PMOS and NMOS transistors for positive voltage conversion, and an NMOS transistor for negative voltage conversion; a specific NMOS transistor for positive voltage conversion is formed in a p-type semiconductor substrate; the PMOS transistors for positive voltage conversion are formed in an n-type first well formed in the p-type semiconductor substrate; and a NMOS transistors for positive voltage conversion other than said specific NMOS transistor, and the NMOS transistor for negative voltage conversion, are formed in a p-type third well, which is formed in an n-type second well formed in the p-type semiconductor substrate.
This embodiment of the invention can thus form the MOS transistors used for voltage conversion in the same p-type semiconductor substrate, and can therefore reduce the external components to capacitors only. It is therefore possible to reduce the overall size while maintaining high power conversion efficiency.
Furthermore, the NMOS transistor for positive voltage conversion is also isolated from a substrate bias effect with the invention described in claim 2, and problems such as an increased threshold value therefore do not occur.
In a third embodiment of the present invention includes a voltage conversion circuit having a plurality of MOS transistors that are switched ON/OFF to charge a capacitance with the input dc voltage, and using this charging voltage to convert the input dc voltage to a specific positive and negative output voltage, wherein: the plural MOS transistors include PMOS and NMOS transistors for positive voltage conversion, and PMOS and NMOS transistors for negative voltage conversion; the NMOS transistors for negative voltage conversion are formed in a p-type semiconductor substrate; the PMOS transistors for positive voltage conversion and PMOS transistors for negative voltage conversion are formed in an n-type first well formed in the p-type semiconductor substrate; and the NMOS transistors for positive voltage conversion are formed in a p-type third well, which is formed in an n-type second well formed in the p-type semiconductor substrate.
This third embodiment of the invention can thus form the MOS transistors used for voltage conversion in the same p-type semiconductor substrate, and can therefore reduce the external components to capacitors only. It is therefore possible to reduce the overall size while maintaining high power conversion efficiency.
Additionally, with the third embodiment of the present invention, substrate biasing to a potential lower than the ground potential is prevented, and PMOS transistors can therefore be used as the MOS transistors producing a negative potential.
Alternatively, a fourth embodiment of the present invention is a voltage conversion circuit having a plurality of MOS transistors that are switched ON/OFF to charge a capacitance with the input dc voltage, and using this charging voltage to convert the input dc voltage to a specific positive and negative output voltage, wherein: the plural MOS transistors include PMOS and NMOS transistors for negative voltage conversion, and PMOS transistors for positive voltage conversion; the PMOS transistors for negative voltage conversion are formed in an n-type semiconductor substrate; the NMOS transistors for negative voltage conversion are formed in a p-type first well in the n-type semiconductor substrate; and the PMOS transistors for positive voltage conversion are formed in an n-type third well, which is formed in a p-type second well formed in the n-type semiconductor substrate.
The fourth embodiment of the present invention can thus form the MOS transistors in the same n-type semiconductor substrate, and can therefore reduce the external components to capacitors only. It is therefore possible to reduce the overall size while maintaining high power conversion efficiency.
Alternatively, the first through fourth embodiments can further include an ON/OFF control means for switching the plural MOS transistors ON/OFF, the ON/OFF control means can be formed in the p-type or n-type semiconductor substrate.
In any of the embodiments, it is also preferably that at least one of the MOS transistors has an offset area in the semiconductor substrate around the gate insulation layer, the offset area being a low concentration impurity layer disposed below a LOCOS layer in the semiconductor substrate.
By providing a low concentration impurity layer as an offset region below a LOCOS (local oxidation of silicon) layer in the invention, the offset region can be made deep relative to the channel area when compared with a configuration in which a LOCOS layer is not formed. As a result, the field around the drain is effectively saturated, the withstand voltage of the drain is increased, and a high withstand voltage can be achieved.
Alternatively, in any of the embodiments, a voltage producing a potential is applied between the semiconductor substrate and second well to assure that they remain in reverse bias condition, or at the same potential during operation. Additionally, and a voltage producing a reverse bias during operation is applied between the second well and third well.
Alternatively, the invention may be implemented with a booster circuit for boosting an input dc voltage n-fold and plurality of MOS transistors, outputting the boosted voltage of the booster circuit as a positive voltage, switching the plural MOS transistors ON/OFF to charge a capacitance with at least the boosted voltage of the booster circuit, and using this charging voltage to produce a negative voltage, wherein: the plural MOS transistors include PMOS and NMOS transistors used for generating the negative voltage; specific NMOS transistors are formed in a p-type semiconductor substrate; the PMOS transistors are formed in an n-type first well formed in the p-type semiconductor substrate; and specific NMOS transistors are formed in a p-type third well, which is formed in an n-type second well formed in the p-type semiconductor substrate.
The invention in this embodiment can thus form the MOS transistors used for voltage conversion in the same p-type semiconductor substrate, and can therefore reduce the external components to capacitors only. It is therefore possible to reduce the overall size while maintaining high power conversion efficiency.
This same embodiment can further include an ON/OFF control means for switching the plural MOS transistors ON/OFF. The ON/OFF control means and the booster circuit can be formed on the p-type semiconductor substrate.
Additionally, at least one of the MOS transistors can have an offset area in the semiconductor substrate around the gate insulation layer, the offset area being a low concentration impurity layer disposed below a LOCOS layer in the semiconductor substrate. This permits the invention to achieve a high withstand voltage.
In this same embodiment, it is preferably that the semiconductor substrate and second well received a voltage to assure that they are maintained reversed biased, or at the same potential, during operation. Also, a voltage producing a reverse bias condition between the second well and third well during operation, is preferably applied.
Lastly, the an n-type fourth well may further be formed in the third well, and a PMOS transistor used for a logic circuit or a PMOS transistor used for generating a negative voltage is formed inside the fourth well.
Means of Resolution
This circuit has the timing signal generator and MOS transistors integrated into the same p-type semiconductor substrate, thus forming an IC chip, with capacitors externally connected to the IC chip. At least one NMOS transistor is formed in the p-type semiconductor substrate, while PMOS transistors are formed in a first well of n-type conductivity formed in the p-type semiconductor substrate. Other NMOS transistors are formed in a third well of p-type conductivity, which is formed in a second well of n-type conductivity formed in the p-type semiconductor substrate.
Other objects and attainments together with a fuller understanding of the invention will become apparent and appreciated by referring to the following description and claims taken in conjunction with the accompanying drawings.